SMIC Adopts Cadence DFM and Low-power Silicon Realization Technology for 65-Nanometer Reference Flow
Cadence Design Systems, Inc. announced that Semiconductor Manufacturing International Corporation (SMIC) has adopted Cadence Silicon Realization products for the design-for-manufacturing (DFM) and low-power technology at the core of SMIC’s 65-nanometer Reference Flow 4.1.
Using Cadence Encounter Digital Implementation System as the foundation, the companies collaborated to provide an integrated end-to-end Silicon Realization flow for 65-nanometer system-on-chip (SoC) designs.
After rigorous evaluation, SMIC selected the Cadence Silicon Realization products based on their hierarchical flow for large-scale designs and superior quality of results. SMIC determined that the tight flow integration across functional, physical, and electrical domains – for estimation, logic design, verification, physical implementation and in-design signoff technologies – provided a significant boost in both designer productivity and ease of use, and produced more deterministic results.
Cadence Silicon Realization technology used in the SMIC flow includes Incisive? Enterprise Simulator, Encounter? RTL Compiler, Encounter Test, Encounter Conformal? Low Power, Encounter Conformal Equivalence Checker, Encounter Digital Implementation System, QRC Extraction, Encounter Timing System, Encounter Power System, Litho Physical Analyzer, Litho Electrical Analyzer, Cadence CMP Predictor and Assura? Physical Verification.
“Our mutual customers can greatly benefit from the Cadence contributions to Reference Flow 4.1, which address two important challenges they face at 65 nanometers — design margins and yields,” said Min Zhu, senior director of design service at SMIC. “Deploying the full end-to-end Cadence Silicon Realization flow for digital design, verification, and implementation along with our reference flow will enable our customers to work more efficiently and productively toward improving silicon quality and shrinking time to market.”
Cadence recently announced a new holistic approach to Silicon Realization that moves chip development beyond its traditional patchwork of point tools to a streamlined end-to-end path of integrated technology, tools, and methodology. The new approach is focused on offering products and technologies that deliver on the three requirements for a deterministic path to silicon: unified design intent, abstraction, and convergence. A key element of the Cadence EDA360 strategy, this approach is aimed at boosting productivity, predictability and profitability while reducing risk.