“Calibre PERC directly addresses an important requirement for electrical rule checking that is currently an unmet need in the industry,” said Yu Wen Tsai, director of design development at Faraday Technology. “Ensuring that we have met all ESD protection rules is critical to the robustness of our designs in portable and high-reliability applications. In the past this has been a lengthy and error-prone process addressed with a combination of manual checks and custom scripts. Calibre PERC is right on target to address this need.”

“We have worked very hard to develop a comprehensive strategy to avoid catastrophic electrical design faults, including developing custom tools,” said Peter Zdebel, senior vice president and chief technology officer for ON Semiconductor. “Checking for illegal connections across multiple voltage domains is a tough problem requiring a very versatile checker. When we looked for a commercially supported product, Calibre PERC was the only one that met our need for a fast, flexible tool that could handle our most complex, multi-power domain needs. Since it is built on the proven Calibre platform, we’re confident it can scale to meet our largest designs now and in the future.”

The Calibre PERC product addresses a range of applications including validating that a circuit has sufficient protection against electrostatic discharge (ESD) events, and helping designers identify inappropriate connections between multiple power supplies in mixed-signal ICs. In the area of ESD verification, the Calibre PERC product ensures the completeness of circuitry needed to protect a device against ESD events, which can cause catastrophic device failures in manufacturing, leave devices susceptible to damage during shipping and assembly, and decrease device life in the field. The Calibre PERC product ensures a higher level of ESD design rule compliance because it goes beyond traditional layout geometry-based checking to enable verification of specific device and interconnect structures and electrical characteristics. It can be used to detect electrical rule violations independent of logical design, for example, identifying the omission of required ESD protection on a schematic or netlist. It can also be used to look for errant signal paths and other soft connection errors such as well connection errors, floating devices, nets, or pins, incorrect voltage supply connections, excessive series pass gates, problem level shifter designs, antenna checks, floating wells, minimum “hot” NWELL width, and many others.

“Increasingly, customers are asking for a solution to determine if their designs are susceptible to electrical failure due to ESD events, and to perform electrical design rule checking in a multi-voltage, mixed-signal environment,” said Joseph Sawicki, vice president and general manager for the Design-to-Silicon division at Mentor Graphics. “The Calibre platform continues to show its versatility as we extend it to address these types of emerging complex circuit verification challenges.”